Wafer Fab Yield Process Engineer

The Senior Wafer Fab Yield Engineer is responsible for driving systematic yield improvement across semiconductor wafer fabrication. This position analyzes manufacturing, inline metrology, defect, wafer-level electrical test, and process data to identify yield-loss mechanisms, determine root causes, and lead implementation of sustainable corrective actions.

The engineer serves as a senior technical resource connecting fab process performance to device and product yield. The role works cross-functionally with Process Engineering, Equipment Engineering, Process Integration, Product/Test Engineering, Failure Analysis, Quality, and Manufacturing to improve yield, reduce variability, and accelerate resolution of complex manufacturing problems.

Responsibilities:

• Lead wafer-fab yield improvement initiatives, identifying and prioritizing the dominant yield-loss mechanisms and converting analysis into actionable improvement projects.
• Analyze wafer probe maps, electrical test/bin data, inline metrology, defect inspection data, equipment/process history, and lot genealogy to isolate sources of systematic and random yield loss.
• Perform correlation, regression, statistical analysis, wafer spatial analysis, trend analysis, and other data-mining techniques to identify relationships between process conditions and electrical yield.
• Lead complex root-cause investigations involving process excursions, recurring yield degradation, wafer-level signatures, equipment effects, materials, and process interactions.
• Partner with Process and Equipment Engineering to translate yield signatures into physical process hypotheses and validate corrective actions.
• Define and execute structured experiments and DOE to validate suspected yield drivers and optimize process windows.
• Use SPC and process-capability analysis to identify process variation and opportunities for improved manufacturing control.
• Correlate WAT, wafer sort, inline process-monitoring, defect, and manufacturing data to identify yield improvement opportunities.
• Work with Failure Analysis teams to develop appropriate physical-analysis plans and translate findings into manufacturing actions.
• Develop analyses and engineering reports that clearly communicate yield trends, excursions, root causes, improvement opportunities, and project status.
• Lead cross-functional technical reviews for significant yield excursions and improvement programs.
• Support new-product and/or technology introduction by identifying yield risks, establishing baseline performance, and accelerating learning during manufacturing ramp.
• Mentor less-experienced engineers in statistical analysis, structured problem solving, yield analysis, and fab troubleshooting.
• Identify opportunities to improve fab-wide yield-analysis methods, data infrastructure, and problem-solving practices.

• Bachelor's degree in Electrical Engineering, Applied Physics, or a related technical discipline.
• Significant engineering experience in semiconductor wafer fabrication, preferably involving yield, process integration, process engineering, product engineering, or device engineering.
• Strong understanding of semiconductor wafer fabrication processes and the relationship between process variation, device characteristics, defects, and electrical yield.
• Demonstrated ability to perform statistical analysis and solve complex manufacturing problems using large manufacturing datasets.
• Experience with statistical/data-analysis tools such as JMP, or comparable platforms.
• Working knowledge of SPC, DOE, process capability, correlation/regression, hypothesis testing, and structured root-cause analysis.
• Ability to communicate complex technical conclusions clearly to engineering and manufacturing organizations.
• Demonstrated ability to lead cross-functional technical problem-solving efforts.

Preferred Qualifications

• Master's degree in Electrical Engineering, Applied Physics,or related discipline.
• Experience with wafer-map and spatial-pattern analysis.
• Experience with semiconductor defect inspection and/or physical failure analysis.
• Experience creating automated yield-analysis or data-mining tools.
• Knowledge of semiconductor device physics and electrical test structures.
• Experience supporting technology or product ramps in a high-volume wafer fabrication environment

Due to the nature of this position and the required access to areas where ITAR-controlled articles and/or technical data may be present, candidates must meet the applicable U.S. person requirements for ITAR access. This…