Director​/Principal Engineer: Digital Verification

About us

Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. Mythic's unique technology makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over USD 125M in a recent funding round and has offices in Palo Alto (CA, USA), Austin (TX, USA), and Bangalore (Karnataka, India).

About

This Role

We are seeking a Director / Principal Engineer of Digital Design Verification to provide technical and strategic leadership for the verification of advanced-node, chiplet-based AI SoCs, with a strong emphasis on analog IP integration and 3D stacking. This role combines deep hands‑on verification expertise with architectural influence, methodology ownership, and team leadership.

The ideal candidate will have a proven track record of delivering first‑time‑right silicon for large, complex SoCs, including high‑speed interconnects, CPUs/AI accelerators, memory subsystems, NVM arrays, Analog modules, and chiplet interfaces.

Here is what you will do

• Own the verification architecture and strategy for one or more complex SoCs / chiplet programs.
• Define and drive block-, subsystem-, and SoC-level verification plans.
• Lead verification of:
  High-performance interconnects (AXI, NoC, PCIe, CXL, UCIe);
  Compute pipelines (CPU, DSP, GPU, AI accelerators);
  Memory subsystems;
  Power management, boot, security, clocking, reset, and DFT features.
• Define and enforce UVM-based verification methodologies.
• Drive adoption of:
  Coverage-driven verification (functional, code);
  Assertion-based verification (SVA);
  Formal verification and static analysis;
  Emulation and FPGA prototyping.
• Own verification KPIs and sign-offs.
• Remain technically hands‑on in critical areas while mentoring verification engineers.
• Work closely with cross functional team members in Arch, Design, PD, Analog, and DFT.
• Build and scale the verification team in Bangalore with a mix of Senior and Junior Verification Engineers.

Here is the background we hope you have

• 15+ years of industry verification experience with a BS/MS/PhD in EE/ECE.
• Deep expertise in:
  System Verilog, UVM, assertions (SVA); functional and code coverage methodologies; debugging of large, multi-million-gate designs.
• Proven experience verifying:
  High-speed interfaces (PCIe/UCIe);
  Cache‑coherent systems and No
  
  Cs; multi-clock, low-power designs (UPF/CPF).
• Strong understanding of the full silicon lifecycle: pre-silicon DV → emulation → post-silicon debug.
• Excellent communication skills across engineering and leadership levels.

The following would be nice to have, but is not required

• Experience with chiplet-based architectures and 2.5D/3D packaging.
• Experience in SoCs with large analog cores.
• Experience in emulation platforms.
• FPGA prototyping.

#LI-Remote At Mythic, we pride ourselves in creating a culture where all employees feel valued and appreciated for the diverse perspectives and backgrounds they bring to the team. We aim to hire smart people, give them the resources they need to do their job well, and then leave the rest up to them. We celebrate individual differences and encourage people to be comfortable bringing their authentic selves to work.

At the end of the day, we are committed to building a diverse workforce where everyone belongs.

Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law.

We look forward to reviewing your application!#J-18808-Ljbffr