Design Verification Engineer

Location:

Palo Alto, CA

Onsite

An early-stage, venture-backed AI semiconductor startup is seeking an experienced Design Verification Engineer to help develop a next-generation chip purpose-built for large language model (LLM) inference.

The company is building a specialized AI accelerator and supporting software stack, offering the opportunity to contribute directly to its first generation of silicon.

This is a highly hands-on role with significant ownership across ASIC/SoC verification, testbench development, functional coverage, debugging, and verification closure. You'll work closely with RTL designers and architects to identify critical design issues, improve verification quality, and ensure silicon readiness.

• Develop and execute verification plans based on architectural specifications and design requirements.
• Identify critical functionality, boundary conditions, corner cases, and potential failure modes across assigned ASIC/SoC blocks and subsystems.
• Build, maintain, and enhance verification environments, test benches, stimulus generation, and checking mechanisms.
• Investigate complex functional failures, trace issues through RTL, and collaborate with design engineers to identify and resolve root causes.
• Develop and execute directed and constrained-random verification tests where appropriate.
• Analyze functional coverage and other verification metrics to identify gaps and drive verification completeness.
• Improve regression workflows, debugging efficiency, and verification infrastructure.
• Support block-level, subsystem-level, and system-level integration verification.
• Drive verification closure and communicate outstanding risks, coverage gaps, and readiness for tapeout.
• Collaborate closely with RTL, architecture, and implementation teams to resolve design issues throughout development.

• Substantial hands-on experience in ASIC or SoC design verification, with demonstrated ownership of verification implementation and debugging.
• Strong understanding of digital logic, hardware interfaces, concurrency, and cycle-level behavior.
• Ability to read, understand, and debug RTL written in Verilog or System Verilog.
• Experience developing verification plans, building test benches, and validating complex digital designs.
• Strong debugging skills, including identifying root causes of complex hardware failures and verifying that fixes fully resolve the underlying issues.
• Experience with functional coverage, regression testing, and verification closure methodologies.
• Ability to collaborate effectively with RTL designers, architects, and other hardware engineers.
• Senior-level technical judgment with a practical, hands-on approach to building and improving verification capabilities.

• Experience verifying AI accelerators, inference ASICs, GPUs, or other high-performance compute silicon.
• Proficiency in System Verilog and Universal Verification Methodology (UVM).
• Experience with System Verilog Assertions (SVA), formal verification, or other advanced verification techniques.
• Background in constrained-random verification, coverage-driven verification, and automated regression environments.
• Experience debugging complex interactions across block and subsystem boundaries.
• Involvement in successful ASIC/SoC tapeouts.
• Experience developing verification infrastructure for first-generation silicon or early-stage semiconductor teams.

• Help develop a next-generation LLM inference accelerator from the ground up.
• Take significant ownership of verification for first-generation silicon.
• Work directly with a highly technical team of RTL designers and computer architects.
• Influence verification strategies, methodologies, and development processes from an early stage.
• Remain deeply hands-on in testbench development, debugging, and verification closure.
• Play a critical role in ensuring the functionality and reliability of a new AI semiconductor platform before tapeout.

The hiring process typically includes two to three conversations focused on previous technical projects, design verification experience, and engineering problem-solving.

References may be requested.

Further details about the company, technology, and roadmap will be shared under NDA as candidates progress through the interview process.

• Medical insurance
• 401(k)
• Vision insurance
• Dental insurance