Design Verification Engineer – Digital RTL & UVM
Listed on 2026-11-04
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Engineering
Test Engineer, Validation Engineer, Electronics Engineer
SpaceX is seeking a Design Verification Engineer (Silicon Engineering) to verify digital ASICs at block and system levels, develop test benches, and drive pre‑ and post‑silicon validation. You will implement UVM or non‑UVM test environments, automate tests with Python and MATLAB, and contribute to chip bring‑up and verification cycles.
The role requires a Bachelor's in EE/CS/CE and 1+ years of design verification and test bench development, with strong coding skills and willingness to work in a
We are looking to fill the Design Verification Engineer – Digital RTL & UVM position at SPACE EXPLORATION TECHNOLOGIES CORP in Palo Alto, CA, United States.
All applications are reviewed carefully by our team.
The position is based in Palo Alto, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 135..
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