Lead DFT Architect -Gen ASICs
Listed on 2026-11-04
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Engineering
Hardware Engineer, Test Engineer, Systems Engineer, Electronics Engineer
Normal Computing is hiring a Design-for-Test (DFT) Engineer to own the DFT architecture and implementation for next‑gen, physics‑inspired ASICs. You will guide scan/ATPG, MBIST, and boundary‑scan strategies and work with RTL, verification, physical design, and silicon product engineering teams.
You will establish DFT methodologies, lead external partners, and ensure designs are ready for manufacturing test, shaping DFT infrastructure for a new silicon class while driving scalable flows and
We have an opening for a Lead DFT Architect for Next-Gen ASICs in Palo Alto, CA, United States within Engineering.
The position is based in Palo Alto, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 180..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
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