AI-Driven Silicon Tapeout Signoff Engineer
Listed on 2026-11-04
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Engineering
Test Engineer, Electronics Engineer, Systems Engineer, Electrical Engineering
Voltai is seeking a senior physical verification engineer in the Palo Alto area to own signoff on real silicon programs and guide AI-driven signoff improvements. You will collaborate with top semiconductor partners and drive reliability checks across block and full-chip levels.
You will perform DRC/LVS/ERC signoffs, IR drop and electromigration analyses, and build automation to streamline tapeouts while partnering with engineering teams to fix signoff issues and ensure robust silicon.
We would love to welcome a new AI-Driven Silicon Tapeout Signoff Engineer to our team in Palo Alto, CA, United States.
We appreciate your interest in this position.
Join Voltai and contribute to our ongoing work.
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This posting is for the AI-Driven Silicon Tapeout Signoff Engineer role at Voltai, based in Palo Alto, CA, United States.
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