RTL Design Engineer in Palo Alto
Listed on 2026-11-04
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Engineering
Electronics Engineer, Hardware Engineer
Job Description Job Description
About VoltaiVoltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the TeamBacked by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & Global Foundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
Aboutthis Role
You'll design and own RTL for production silicon, from microarchitecture to signoff-ready code. You'll work on real chip programs with leading semiconductor companies while helping Voltai's AI learn to write, review, and debug RTL the way the best designers do.
What You’ll DoOwn microarchitecture and RTL implementation for IP blocks and subsystems in System Verilog.
Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
Partner with verification and formal teams on test plans, assertions, and coverage closure.
Debug complex functional and timing issues across simulation, emulation, and silicon.
Review and evaluate AI-generated RTL, and help define what correct, high-quality design looks like.
Work directly with customer design teams when needed.
5+ years of RTL design experience on chips that taped out.
Expert System Verilog/Verilog and strong microarchitecture skills.
Hands-on experience with lint, CDC, synthesis, and timing-aware design.
Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar).
Python or Tcl scripting.
Experience writing SVA or working with formal verification.
Low-power design (UPF, clock and power gating).
Interest in AI-assisted design tools.
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