Lead DFT Architect -Gen ASICs

Normal Computing is seeking a Design-for-Test (DFT) Engineer to own chip-level DFT architecture and implementation for next-generation ASICs, from RTL through tapeout. The role demands leadership, strong hands-on skills in scan, ATPG, MBIST, and boundary-scan, with collaboration across RTL, verification, physical design, and silicon product engineering.

You will guide external partners, establish scalable DFT flows, and ensure manufacturing test readiness, while maintaining power, performance,

Step into the Lead DFT Architect for Next-Gen ASICs role at Normal Computing Corporation in Palo Alto, CA, United States and grow with us.

This role, Lead DFT Architect for Next-Gen ASICs at Normal Computing Corporation, could be your next move.

Are you ready to take on the Lead DFT Architect for Next-Gen ASICs role at Normal Computing Corporation?

We would love to welcome a new Lead DFT Architect for Next-Gen ASICs to our group in Palo Alto, CA, United States.