Lead RTL Design Engineer: AI Silicon Tapeout
Listed on 2026-11-05
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Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer, Test Engineer
Normal Computing is seeking a Lead RTL Design Engineer to head RTL development for thermodynamic hardware. You will own RTL from microarchitecture to tapeout, write System Verilog, and guide verification and physical design to meet timing and area goals.
As a senior leader, you will shape architecture, refine design methodology, and drive cross‑functional alignment with architects, verification, and PD, while helping hire and mentor the team in a fast‑paced, collaborative environment.
We would love to welcome a new Lead RTL Design Engineer: AI Silicon Tapeout to our team in Palo Alto, CA, United States.
The advertised compensation is 180..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Lead RTL Design Engineer: AI Silicon Tapeout role in the description above.
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