IC Package Design Engineer

Rivianis on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract.

As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations.

We are seeking an IC Package Design Engineer to join our ASIC team. In this role, you will lead the physical layout, modeling, and analysis of advanced semiconductor packaging solutions for high-performance integrated circuits (ICs). You will collaborate closely with cross-functional teams, including IC Design, Signal/Power Integrity (SI/PI), PCB Layout, Mechanical, Thermal, and Test Engineering, as well as substrate vendors and OSAT partners to deliver robust, cost-effective packaging from concept through volume production.

• End-to-End Package Layout:
  Own physical layout execution, including die placement, bump assignment, floor planning, ball map optimization, bump-to-ball fan-out planning, stack-up definition, and layer planning.
• Advanced Packaging Implementations:
  Design and develop advanced IC packaging solutions, including flip-chip BGA (FCBGA), System-in-Package (SiP), and 2.5D/3D IC architectures (e.g., interposers, CoWoS, EMIB, FOWLP).
• Silicon, Package & Board Co-Design:
  Partner closely with silicon and system teams to align on die/package/PCB co-design, floor planning, ball map, and interposer routing.
• High-Speed & Power Delivery Network: define and route high speed interfaces (e.g., DDR, PCIe, Ser Des), design robust Power Delivery Networks (PDN) with high di/dt requirement
• EDA Tooling:
  Create, manage, and validate complex package layouts using industry-standard EDA tools (e.g., Cadence APD/SiP, Cadence Virtuoso, Synopsys 3
  
  DICC, Siemens Xpedition).
• Verification & Signoff:
  Run Design Rule Checking (DRC), Layout vs. Schematic (LVS) checks, netlist verification, and strict Design for Manufacturing (DFM/DFT) reviews.
• Manufacturing Collateral:
  Generate and validate complete manufacturing collateral (Gerbers, ODB++, BOMs) for tapeout and manufacturing release.
• Multi-Disciplinary Convergence:
  Work directly with SI/PI, thermal, and mechanical engineering teams to achieve design convergence across power, signal integrity, thermal, and mechanical reliability constraints.
• Vendor & OSAT Integration:
  Interface with foundries, substrate vendors, and OSAT partners to evaluate design feasibility, select packaging materials and design rules, maximize manufacturing yield, and execute smooth tapeouts.
• Bring-up & Test Support:
  Assist in lab bring-up, debugging, and silicon validation for packaged devices; collaborate with test engineering teams on probe card and test socket interface design.
• Workflow Automation:
  Develop and implement scripting tools (e.g., Python, Tcl, Perl, MATLAB) to automate layout flows and enhance design efficiency.
• AI/ML Innovation:
  Explore and drive adoption of AI/ML-enabled methodologies (e.g., predictive analytics, layout optimization, automated rule checks) to scale productivity and decision-making.

• Education:
  
  B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, Mechanical Engineering, or a related field.
• Experience:
  
  3+ years (5+ years preferred) of hands-on experience in semiconductor package and substrate layout design, particularly for high-speed (Ser Des) and high di/dt IC applications.
• EDA Tools Proficiency:
  Proven expertise with industry-standard packaging EDA tools such as Cadence Allegro…