Physical Design Engineer

An early-stage, venture-backed AI semiconductor startup is seeking an experienced Physical Design Engineer to help develop a next-generation chip purpose-built for large language model (LLM) inference.

The company is building a specialized AI accelerator and supporting software stack, offering the opportunity to contribute directly to its first generation of silicon.

This is a hands‑on engineering role with significant responsibility across ASIC physical implementation, floor planning, timing closure, power optimization, and tapeout readiness. You'll work closely with RTL, architecture, and implementation teams to ensure designs meet physical constraints and performance targets.

• Contribute to floor planning and physical implementation of complex digital ASIC designs, translating architectural requirements into practical placement and connectivity decisions.
• Analyze and optimize power, performance, and area (PPA) trade-offs throughout the implementation process.
• Identify physical design constraints that require upstream RTL or architectural modifications.
• Investigate and resolve complex physical implementation issues involving floor planning, timing, power, and design closure.
• Collaborate with RTL and microarchitecture engineers to ensure front‑end design decisions align with physical implementation requirements.
• Work with internal engineering teams and external implementation partners to maintain consistent design assumptions and technical handoffs.
• Support physical verification, implementation signoff, and tapeout readiness.
• Track outstanding implementation issues, identify technical risks, and drive engineering solutions through closure.

• Substantial hands‑on experience in digital ASIC physical design and backend implementation.
• Demonstrated ownership of meaningful physical implementation work on complex ASIC or SoC designs.
• Strong understanding of floor planning, placement, connectivity, timing constraints, and physical design optimization.
• Experience analyzing power, performance, and area trade‑offs throughout the implementation process.
• Proven ability to investigate and resolve challenging floor planning, power, timing, or design closure issues.
• Strong understanding of how RTL and microarchitecture decisions influence backend implementation feasibility.
• Experience collaborating with RTL, architecture, and physical implementation teams.
• Senior‑level technical judgment with a willingness to remain deeply hands‑on in physical design and debugging.

• Experience with AI accelerators, inference ASICs, GPUs, or other high‑performance compute processors.
• Familiarity with synthesis‑to‑layout implementation flows.
• Experience with static timing analysis (STA), timing closure, and physical optimization.
• Knowledge of power integrity, power distribution networks, and physical verification.
• Involvement in successful ASIC/SoC tapeouts.
• Experience working with external backend design or implementation partners.
• Background in first‑generation silicon development or early‑stage semiconductor startups.

• Help develop a next‑generation LLM inference accelerator from the ground up.
• Take meaningful ownership of physical implementation for first‑generation silicon.
• Work closely with a highly technical engineering team across architecture, RTL, and backend design.
• Influence design decisions early, ensuring physical constraints are considered throughout development.
• Remain highly hands‑on while contributing to major technical and implementation decisions.
• Play a critical role in bringing an ambitious AI semiconductor platform toward its first tapeout.

The hiring process typically includes two to three conversations focused on previous technical projects, physical design experience, and engineering problem‑solving.

References may be requested.

Further details about the company, technology, and roadmap will be shared under NDA as candidates progress through the interview process.