Senior RTL Design Engineer AI Accelerator Systems

Delos Data is seeking a Senior RTL Design Engineer to design, implement, and deliver high-quality RTL for complex digital systems in our Palo Alto office. You will translate architectural specs into scalable microarchitectures using Verilog/System Verilog, collaborating with architecture, verification, and physical design teams to meet timing, power, and area goals.

Ideal candidates have 5+ years in RTL design, strong design fundamentals, and hands-on experience with synthesis, linting, and

This is a great position to take on the Senior RTL Design Engineer for AI Accelerator Systems role at Delos Data.

We aim to respond to suitable candidates as soon as possible.

Full responsibilities and requirements are described in the listing above.

Learn more about the Senior RTL Design Engineer for AI Accelerator Systems role in the description above.

We appreciate your interest in this position.