Digital Verification Engineer – PCIe/RISC-V, UVM expert
Listed on 2026-10-20
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Engineering
Test Engineer, Quality Engineering, Validation Engineer
Arago is seeking a senior verification engineer to ensure the functional integrity, performance, and reliability of next-generation optical chips. You will wield System Verilog, UVM, and modern verification environments to verify high-speed interfaces and PCIe components.
You will collaborate with architects, designers, and customers, plan end-to-end ASIC verification, and support bring-up and post-silicon validation.
We are looking to fill the Digital Verification Engineer – PCIe/RISC-V, UVM expert position at Arago in Paris, TX, United States.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in Paris, TX, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 120..
We aim to respond to suitable candidates as soon as possible.
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