Senior ASIC Physical Design Engineer: Tapeout & Timing Lead

Analog Devices, Inc. in the United States seeks a Senior Physical Design Engineer to lead complex digital and mixed‑signal IC implementation, from floor planning to tapeout.

You will drive timing closure, power optimization, and physical verification while collaborating with RTL, DFT, STA, and packaging teams to ensure robust silicon delivery. The role demands deep expertise in backend flows, signoff readiness, and mentoring of engineers, with a focus on high‑quality, efficient methodology and

This role is for the Senior ASIC Physical Design Engineer:
Tapeout & Timing Lead role at 1010 Analog Devices Inc.

We aim to respond to suitable candidates as soon as possible.

Full responsibilities and requirements are described in the listing above.

Learn more about the Senior ASIC Physical Design Engineer:
Tapeout & Timing Lead role in the description above.