Lead Power Packaging Engineer – SiP & Wafer-Level Tech
Listed on 2026-10-31
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Engineering
Electronics Engineer, Systems Engineer -
IT/Tech
Systems Engineer
Renesas Electronics Corp. is seeking a senior Package Technology Development leader to drive R&D and NPI for AI/Datacenter infrastructure power packaging.
You will manage OSAT/CM collaborations, define roadmaps, and optimize processes to meet stringent product qualifications. The role requires 15 to 20 years in package development with emphasis on power SiP/module and wafer-level/flip-chip packaging, plus strong analytical and presentation skills.
This is a strong role to take on the Lead Power Packaging Engineer – SiP & Wafer-Level Tech role at Renesas Electronics Corp.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Lead Power Packaging Engineer – SiP & Wafer-Level Tech role in the description above.
We appreciate your interest in this position.
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