Digital Design Engineer – ASIC​/RTL

Location: Cambridgeshire, UK |
Employment Type: Permanent, Full-Time

Join an established international semiconductor company developing advanced integrated circuit solutions for demanding electronic applications.

As Staff Digital Design Engineer – ASIC / RTL, you’ll take a technical lead role in developing digital functionality for mixed-signal ASICs, working across the full design lifecycle from architecture and RTL development through verification, synthesis and physical implementation. You’ll collaborate with multidisciplinary engineering teams, influence key design decisions and drive improvements in digital design methodologies.

This is an opportunity to combine hands-on technical expertise with leadership, delivering high-quality, power-efficient digital designs from concept through to production.

What you’ll do as a Staff Digital Design Engineer:

• Develop and review synthesisable System Verilog RTL for mixed-signal ASICs, from specification through to production.
• Support product definition, feasibility studies, architectural decisions and FPGA-based emulation.
• Develop test benches, behavioural models and regression environments for thorough functional verification.
• Execute digital synthesis and optimise designs for power, performance and area (PPA).
• Define and implement design-for-test (DFT) strategies, including scan insertion, ATPG and test coverage optimisation.
• Oversee physical implementation, place-and-route and post-layout timing closure.
• Collaborate with analogue, product definition and test engineering teams to ensure successful system integration.
• Produce technical documentation, contribute to design reviews and drive improvements in design flows and methodologies.
• Provide technical guidance and leadership to other engineers.

What you’ll bring as a Staff Digital Design Engineer:

• An MSc, MEng or PhD in Electronics Engineering or a related discipline, or equivalent experience.
• At least five years’ experience in digital IC design using standard-cell libraries.
• Strong System Verilog and RTL design skills, with a solid understanding of ASIC design flows and EDA tools.
• Experience with synthesis, timing constraints, place-and-route and timing closure.
• Knowledge of DFT methodologies, including scan architectures and ATPG.
• Experience optimising digital designs for power, performance and area.
• Understanding of mixed-signal integration and practical laboratory debugging using equipment such as mixed-signal oscilloscopes.
• Proficiency in TCL and/or Python scripting.
• Strong documentation, problem-solving and cross-functional communication skills.
• The ability to provide technical leadership and drive continuous improvement.