ASIC Physical Design Engineer - Power, Senior

Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon.

In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market.

Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.

As a Senior Physical Design Engineer
- Power, you will drive power estimation, optimization, and verification for key blocks and subsystems across Positron's AI accelerator roadmap. Working alongside senior technical leadership, you will execute and help improve our power methodology from architectural modeling through silicon validation, helping us deliver industry-leading performance-per-watt while meeting aggressive power and thermal constraints.

Power Architecture & Strategy

• Contribute to the overall chip power strategy, and own power approaches for assigned blocks and subsystems across dynamic power, leakage, clock power, memory power, interconnect power, idle power, and peak power.

Power Modeling

• Build and maintain accurate power models across the development lifecycle, from early architectural estimation through RTL and gate-level estimation.
• Perform vector-based and activity-driven power analysis to validate estimates against real workload behavior.

Power Optimization

• Implement and drive power optimization techniques including clock gating, operand isolation, power gating, voltage islands, and multi-Vt optimization.
• Identify and apply memory, pipeline, toggle-reduction, and data-movement optimizations, including approaches tailored to AI workloads.
• Give RTL teams actionable feedback to reduce power early in the design cycle.

Power Integrity

• Work with the backend team on IR drop, electromigration (EM), power distribution, and power grid analysis.
• Develop and maintain UPF/CPF specifications for assigned domains, including power domains, isolation, retention, power-on sequencing, and reset sequencing.
• Run power-aware simulation and UPF verification for your blocks.
• Support reset verification, low-power state validation, wakeup validation, and power sequencing verification.

Cross-Functional Collaboration

• Partner with Architecture, RTL, Backend, Firmware, Thermal, Packaging, and System Engineering teams to align power decisions across the chip development flow.

AI-Enabled Engineering

• Use AI-driven tools to improve power analysis, regression triage, power anomaly detection, activity clustering, and identification of optimization opportunities.

• 8+ years of ASIC design or implementation experience, with a significant focus on power.
• Hands-on experience with UPF/CPF power specification and verification flows.
• Strong proficiency with Prime Power and Joules or equivalent power analysis tools.
• Experience working with advanced process nodes.
• A solid grasp of RTL design and its impact on chip power.
• Track record of contributing to power targets on production silicon.
• Strong Tcl and/or Python scripting skills for analysis and automation.

• Experience with AI accelerator architectures.
• Familiarity with LPDDR and HBM memory interfaces.
• Working knowledge of PCIe.
• Experience with dynamic voltage and frequency scaling (DVFS).
• Exposure to thermal modeling.
• Hands-on experience with silicon power validation.
• Experience mentoring junior engineers or leading power efforts for a subsystem.

While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. This job description is a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.