Senior Product, Test and Yield Enhancement Engineer - Taiwan

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups.

OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Senior Product, Test and Yield Enhancement Engineer — Taiwan

Cerebras is seeking a senior VLSI product and test engineer with 10+ years of experience in semiconductor testing, failure analysis and yield enhancement. In this role, you will drive the test strategy for future generations of the Cerebras Wafer Scale Engine in Taiwan. Your work will span AI processors, high-speed I/O and memory; including ATE test development, manufacturing-data analysis, wafer disposition, defect characterization, failure isolation and yield improvement.

• Develop and optimize production test programs for wafer-scale AI processors.
• Drive high-volume manufacturing testing in partnership with foundries and outsourced semiconductor assembly and test providers (OSATs).
• Implement and optimize design-for-test strategies, including scan, built-in self-test (BIST), automatic test-pattern generation (ATPG) and functional testing.
• Analyze automated test equipment (ATE), Shmoo, parametric and defect data to improve yield and fault tolerance.
• Develop failure-analysis and fault-isolation methods for defective cores, tiles and other functional blocks.
• Build efficient wafer-level test flows for massively parallel compute, mesh and network-on-chip architectures, and die-to-die interconnects.
• Partner closely with DFT, architecture, design, performance, software and manufacturing teams.
• Optimize voltage-frequency operating limits, current, thermal behavior, power delivery and parallel die-testing capabilities.
• Support wafer and lot disposition decisions throughout high-volume manufacturing.

• BS or MS in Electrical Engineering, Computer Engineering or a related field.
• 10+ years of semiconductor product or test-engineering experience supporting highly integrated devices.
• Strong experience in test development, silicon debug, test optimization and yield improvement.
• Experience testing large parallel processors, GPUs, CPUs or networking ASICs incorporating SRAM, DDR/DRAM or HBM.
• Expert-level, hands-on experience with the Advantest V93000 platform;
  Teradyne experience is a plus.
• Experience specifying, designing, developing and debugging load boards and probe cards for advanced production-test and DFT requirements.
• Strong cross-functional collaboration and probl