Senior Layout Design Engineer Level Chip Planning Lead

SiTime Corporation is seeking a Sr. Layout Design Engineer to lead top-level chip-planning and perform comprehensive CMOS/BiCMOS layout work.

You will coordinate with offshore teams, mentor junior engineers, and help develop standard layout methodologies across sites, contributing to build processes and achieving high layout quality. The role involves remote interfacing with global teams, floor planning, layout verification (DRC/LVS/ERC), and chip-level integration.

We are currently recruiting a Senior Layout Design Engineer – Top‑Level Chip Planning Lead for our team in United States.

This Full Time opportunity is for the Senior Layout Design Engineer – Top‑Level Chip Planning Lead role at SiTime Corporation.

We are seeking a motivated Senior Layout Design Engineer – Top‑Level Chip Planning Lead to join SiTime Corporation in United States.

Consider building your career as a Senior Layout Design Engineer – Top‑Level Chip Planning Lead at SiTime Corporation.