Speed I​/O PHY Architect

Position: High-Speed I/O PHY Architect
#
** Welcome!**## .High-Speed I/O PHY Architect page is loaded## High-Speed I/O PHY Architect locations:
US, California, Folsom:
US, Oregon, Hillsboro:
US, California, Santa Clara:
US, Arizona, Phoenix time type:
Full time posted on:
Posted Todayjob requisition :
JR0277989#
** Job Details:**##

Job Description:

Join Our Team as a High-Speed I/O PHY Architect.

Key Responsibilities
* Architectural Leadership:
Lead the architectural definition and integration of high-speed PHYs for client SoCs, including PCIe, CXL, USBx (e.g., eUSB2, USB3, USB4), Display, MIPI (D-PHY, C-PHY, M-PHY), Ethernet, and TSN. Collaborate with platform and product architects to analyze requirements and define critical performance, power, and area specifications to ensure the success of our products.
* IP Evaluation:
Conduct technical evaluations of both internal and external PHY IPs, analyzing their performance characteristics against product requirements, and ensuring strategic alignment with overall product goals. Define detailed IP requirements, lead vendor engagement, and make strategic IP selection recommendations based on technical feasibility, cost-effectiveness, and long-term roadmap alignment.
* Technology Vision:
Proactively research and evaluate emerging high-speed I/O technologies, industry trends, and evolving standards. Identify and champion opportunities to incorporate these advancements into our product roadmap, enhancing performance, power efficiency, and feature sets, and positioning our products for competitive advantage.
* Technical Documentation:
Create clear and comprehensive architecture specifications and rigorous integration guidelines. Provide review and constructive feedback on related architectural specifications to ensure alignment with overall SoC goals.
* Technical Mentorship and

Collaboration:

Provide technical guidance and mentoring to junior engineers, fostering their growth and contributing to the overall team expertise. Champion a collaborative environment across multiple teams.
* Post-Silicon Leadership:
Serve as a technical lead in the post-silicon debug and validation of high-speed I/O interfaces, leading taskforces and driving the resolution of complex issues. Oversee the validation process to ensure seamless and high-quality implementations.

Additional

Skills:

* Demonstrated strategic acumen with proven effectiveness in collaborating with senior technologists and business leaders across organizational boundaries.
• Demonstrated ability to network with and influence a broad range of stakeholders##
*
* Qualifications:

** Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

•
* BS degree in Electrical/Computer Engineering with a minimum of 15 years of experience.
* Master's or PhD degree in Electrical/Computer Engineering with minimum 12 years of experience

Preferred Qualifications:

* High familiarity with industry trends within the HSIO domain and the ability to map them to Intel roadmap/products and segment strategies.
* We look forward to welcoming a dynamic and innovative High-Speed I/O (PHY) Architect to our team. Apply now and be a part of shaping the future of our client SoC technology.
* Prior hands-on experience in High-Speed IO PHY Architecture and Design.
* Strong knowledge in the interoperability of HSIO PHYs within the PCIe, SATA, Ethernet, USB2, USB3, USB4, Display or MIPI IO Controller subsystems
* Strong technical leadership and communication skills## Job Type:Experienced Hire##

Shift: Shift 1 (United States of America)## Primary

Location:

US, California, Folsom## Additional Locations:

US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro## Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.## Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of Trust This role is a Position of Trust.

Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this…