Senior Layout Designer

Job Details

Senior Layout Designer – Intel Corporation

Designs, implements, and verifies the layout design of test structures and circuits that enable the development of Intel’s leading‑edge silicon technologies. The test structures model Quality and Reliability (QnR) parameters essential to the qualification life cycle for each technology. The role collaborates with Technology Development (TD), Design Technology Platform (DTP), and a world‑class team of QnR engineers to understand, define, and execute the requirements of new trailblazing Test Chips.

• Develop custom layout designs of analog blocks, complex digital, mixed‑signal blocks, standard cell libraries, or memory compilers (e.g., bitcells, SRAMs, Register Files).
• Perform detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding.
• Conduct complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), self‑heat, ESD, and other reliability checks. Use custom auto‑routers and placers to efficiently construct layout.
• Provide feedback to circuit design engineers for new feature feasibility studies and implement circuit enhancement requests.
• Develop and drive new innovative layout methods to improve productivity and quality.
• Troubleshoot a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.

• Design, implement, verify, and support enablement and adoption of hardware design tools, flows, and methodologies.
• Define methodologies for hardware development related to technology node and EDA tool enabling.
• Create and verify unique hardware designs, assemble design platforms, and integrate components into hierarchical systems to provide deployment coverage for end‑to‑end EDA tool testing on new technology nodes.
• Develop, test, and analyze engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance.
• Support development and enhancement of platforms, databases, scripts, and tools flows for design automation.
• Build deep understanding of digital design, verification, structural and physical layout, full‑chip integration, power, and performance clocking, and/or timing to enhance future TFM development.
• Collaborate with EDA vendors on defining and early testing of next‑generation design tools.

Minimum Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field and 6+ years of experience OR a Master’s degree and 4+ years of experience OR a PhD and 2+ years of experience in layout design & Cadence Virtuoso.

Preferred Qualifications

• 6+ years of experience in CMOS VLSI design concepts, flows, and EDA tools.
• Programming/scripting in C/C++, Python.
• UNIX/Linux operating systems.
• 8+ years of experience in layout design, Cadence Virtuoso Layout Suite, layout debug (DRC, LVS).
• 4+ years of experience in EDA Tools, Flows, and Methodology (TFM) development.
• 1+ year of experience with Cadence SKILL programming languages.
• Experience leading and coordinating small/medium size group of layout designers.
• Strong initiative, analytical/problem‑solving skills, communication skills, team working skills, ability to multitask and work with a diverse team located in different geos.

Experienced Hire

Shift 1 (United States of America)

Primary: US, Oregon, Hillsboro
Additional: US, Arizona, Phoenix

Intel Foundry – state‑of‑the‑art semiconductor manufacturing, AI‑era silicon process & packaging, customer‑centric design and production.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

N/A

The role offers a competitive pay, stock, bonuses, and comprehensive benefit programs including health, retirement, and vacation. For more information, visit the benefits page.

Annual Salary Range (US): $121,050 – $227,620

Hybrid – split time between on‑site at the assigned Intel site and off‑site.