Neuromorphic Front-End Silicon Lead

The Opportunity For nearly a decade, Intel’s Neuromorphic Computing Lab-together with a global ecosystem of 250+ research groups-has explored architectures, algorithms, and software inspired by the brain’s extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach. Now, we’re entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators.

If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel’s neuromorphic computing technology with the versatility demanded by modern AI workloads. Position Overview As our silicon team grows, we are seeking a front-end silicon lead to manage both the design and verification of our neuromorphic chiplets and IP.

This principal-level role calls for a talented technical leader with a track record of realizing new processor and accelerator architectures, plus strong SoC integration experience including high-speed interfaces such as Ethernet, PCIe/UCIe, and memory controllers. Your multidisciplinary team will turn emerging neuromorphic and AI accelerator concepts into robust, manufacturable silicon. First-principles thinking and an openness to learning new technologies and methodologies, such as asynchronous design and AI automation, are essential.

• Engage with architects and AI researchers to identify hardware innovations and optimizations, and translate them into implementable microarchitectures.
• Lead a team responsible for design implementation and verification through post-silicon validation.
• Partner with physical/custom design engineers, often first prototyping blocks through place-and-route prior to hand-off, and co-design critical custom circuits such as memories to achieve the best KPIs.
• Evaluate, select, and integrate internal and external IP, including I/O interfaces.
• Work with software and systems teams to enable development long before tape-out and ensure smooth post-silicon bring-up.
• Mentor engineers and strengthen design and verification practices as the program scales.

• MS in Electrical/Computer Engineering, Computer Science, or a related field.
• 10+ years of hands‑on design experience in processors, accelerators, SoCs, or custom ASICs.
• 5+ years of experience with RTL design (Verilog/System Verilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV).
• 3+ years leading silicon design and/or verification teams.

• PhD with a research background in hardware acceleration, especially AI.
• Experience with advanced packaging and heterogeneous integration technologies (e.g., chiplets, UCIe, 2.5D/3D).
• Experience with asynchronous design methods and custom memory/circuit co‑design.
• Experience with pre-silicon enablement via emulation or FPGA prototyping.
• Experience with low‑power (UPF) methods and security features such as Root of Trust and secure boot.
• History of technical ownership on multiple product tape‑outs.

Experienced Hire

Shift 1 (United States of America)

US, Oregon, Hillsboro

US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin

All qualified applicants will receive consideration for employment without regard to race, color,…