Senior DFT​/DFM Logic Engineer – ASIC Tape- Expert

Intel Corporation's Foundry Services group in the United States seeks a Senior DFT Logic Design Engineer to advance DFT/DFM insertion, ATPG validation, and tape-out readiness for advanced CMOS processes. You will collaborate with internal and external design teams, AI/EDA vendors, and validation groups to deliver robust DFT flows.

Join a team that drives high-quality silicon in aerospace, defense, and government applications, developing training materials and documenting methodologies for

The Senior DFT/DFM Logic Engineer – ASIC Tape-out Expert position in the IT & Technology, Engineering field is open for applications.

This role, Senior DFT/DFM Logic Engineer – ASIC Tape-out Expert at Intel Corporation, could be your next move.

Are you ready to take on the Senior DFT/DFM Logic Engineer – ASIC Tape-out Expert role at Intel Corporation?

We would love to welcome a new Senior DFT/DFM Logic Engineer – ASIC Tape-out Expert to our team in Phoenix, AZ, United States.