Principal SerDes Architect AI Interconnects
Listed on 2026-10-27
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Engineering
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Design & Architecture
Celero Communications, Inc. is seeking a Principal Ser Des Design Engineer to lead architecture and design of Ser Des for next-generation transceivers powering AI, data center interconnects, and high-speed compute fabrics.
You will shape roadmaps, select topologies, and drive architecture decisions with cross-functional teams. Responsibilities include defining block-level specifications, conducting system-level modeling with MATLAB and System Verilog, designing high-performance analog/mixed-signal
The following opening is for a Principal Ser Des Architect for AI Interconnects with Celero Communications, Inc.
Our team is growing, and we are hiring a Principal Ser Des Architect for AI Interconnects in United States.
This Full Time opening is for the Principal Ser Des Architect for AI Interconnects role at Celero Communications, Inc.
We are seeking a motivated Principal Ser Des Architect for AI Interconnects to join Celero Communications, Inc. in United States.
Consider building your career as a Principal Ser Des Architect for AI Interconnects at Celero Communications, Inc.
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