ASIC Power Engineer, Principal

Role Overview

This role owns power architecture, estimation, optimization, and verification across Positron’s AI accelerator roadmap. You will define power methodology from architectural modeling through silicon validation, ensuring industry-leading performance-per-watt while meeting aggressive power and thermal constraints.

Power Architecture & Strategy

• Own the overall chip power strategy, defining approaches for dynamic power, leakage, clock power, memory power, interconnect power, Ser Des power, idle power, and peak power.

Power Modeling

• Develop accurate power models across the full development lifecycle, from early architectural estimation through RTL and gate-level estimation.
• Perform vector-based and activity-driven power analysis to validate estimates against real workload behavior.

Power Optimization

• Drive power optimization techniques including clock gating, operand isolation, power gating, voltage islands, and multi-Vt optimization.
• Apply memory, pipeline, toggle-reduction, and data-movement optimization techniques, including approaches tailored to AI workloads.

Power Integrity

• Partner with the backend team on IR drop, electromigration (EM), power distribution, and power grid planning.
• Define power-on sequencing, power domains, reset sequencing, isolation, retention, and UPF/CPF specifications.

Power Verification

• Own power-aware simulation and UPF verification.
• Lead reset verification, low-power state validation, wakeup validation, and power sequencing verification.

Cross-Functional Collaboration

• Partner closely with Architecture, RTL, Backend, Firmware, Thermal, Packaging, and System Engineering teams to align power decisions across the full chip development flow.

AI-Enabled Engineering

• Use AI-driven tools to improve power analysis, regression triage, power anomaly detection, activity clustering, and identification of optimization opportunities.

• 12+ years of ASIC design experience.
• Deep expertise in low-power design techniques and methodologies.
• Hands-on experience with UPF/CPF power specification and verification flows.
• Expert-level proficiency with Prime Power and Joules or equivalent power analysis tools.
• Strong background working with advanced process nodes.
• A solid grasp of RTL design and its impact on chip power.
• Proven experience achieving aggressive power targets in production silicon.

• Experience with AI accelerator architectures.
• Familiarity with LPDDR and HBM memory interfaces.
• Working knowledge of PCIe.
• Experience with dynamic voltage and frequency scaling (DVFS).
• Exposure to thermal modeling.
• Hands-on experience with silicon power validation.

While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.

Success in this role looks like power estimates that consistently predict silicon behavior, sustained performance-per-watt leadership across Positron’s product line, and a power architecture that is reused and extended across future generations of chips.

• Shape the power architecture foundation for a new generation of AI inference accelerators, with direct influence on Positron’s performance-per-watt leadership.
• Work at the frontier of silicon and AI, on chips built specifically for the demands of large-scale LLM inference.

The base salary range for this role is $200,000 – $300,000.

Please note that the figures provided represent the base salary…