Lead SystemVerilog/UVM Verification Architect – DDR
Listed on 2026-10-17
-
Engineering
Test Engineer, Hardware Engineer
Renesas Electronics Corp. in Plano, TX is seeking a Principal Design Verification Engineer to lead verification strategy and execution for next‑generation memory interface products, including data buffers and DDR IP.
You will own verification of complex digital designs at the block and system levels, collaborating with RTL/design engineers to ensure quality and sign‑off. The ideal candidate has deep System Verilog and UVM experience, strong technical leadership, and a track record of driving
We would love to welcome a new Lead System Verilog/UVM Verification Architect – DDR6 to our organisation in Plano, TX, United States.
The position is based in Plano, TX, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 140..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).