Principal Power Architect

Invent the future with us.

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

Join us at Ampere and work alongside a passionate and growing team-we’dlove to have you apply!

Ampere is looking for a Principal Power Architect to drive power modeling, analysis, optimization, management, convergence, and validation across CPU, AI accelerator, memory, I/O, and interconnect designs.

This role works across architecture, microarchitecture, RTL, implementation, firmware, validation, and silicon.

The ideal candidate has strong CMOS fundamentals and experience turning workloads, power data, and architectural tradeoffs into actionable design decisions.

The role may include pre-silicon power analysis, post-silicon characterization, power-management feature enablement, power modeling and power attainment.

• Define power targets, budgets, operating points, and optimization strategies for CPU, AI accelerator, and SoC blocks.
• Develop and maintain architectural, activity-based, RTL, gate-level, emulation, and silicon power models.
• Set up and run RTL- and gate-level power analysis, develop benchmarks and tests, and review results for opportunities at the architecture, RTL, synthesis, and implementation levels.
• Characterize CPU, memory, PCIe, networking, storage, AI training, and AI inference workloads to identify power and performance bottlenecks.
• Drive power/performance/area/thermal tradeoff studies and power convergence across design & implementation phases.
• Develop automation, data-processing flows, dashboards, and analysis scripts using Python, TCL, Perl, or similar languages.
• Use AI for productivity to accelerate workload characterization, power modeling, anomaly detection, regression analysis, test generation, documentation, and power-management decisions.
• Validate AI-generated results against engineering data and design requirements.
• Drive power-management techniques including clock gating, power gating, DVFS, adaptive voltage scaling, retention, low-power modes, and workload-aware power management
• Lead or support post-silicon power and voltage-frequency characterization across domains and blocks.
• Work with ATE, production, firmware, validation, and systems teams on power management settings, AVS, voltage-frequency specifications, silicon binning, and SKU definition.
• Correlate pre-silicon estimates with silicon measurements, investigate gaps, and improve models and methodologies.
• Communicate findings, drive closure, and build consensus across architecture and design, verification, physical design, firmware, performance, and product teams.

• Experience in semiconductor power analysis, modeling, optimization, power management, workload characterization, or silicon validation.
• Strong understanding of CMOS power fundamentals and power-reduction techniques.
• Knowledge of CPU, AI accelerator, memory, I/O, interconnect, and processor workload behavior.
• Experience with RTL and gate-level power-analysis tools and methodologies; familiarity with tools such as Spyglass, Power Artist, Joules, Prime Power, or equivalent is useful.
• Experience with emulation, FPGA, silicon measurement, telemetry, or power/performance correlation is valuable.
• Experience with voltage-frequency characterization, AVS, silicon binning, SKU definition, or Power-management firmware is a plus.
• Strong programming and scripting skills in Python;
  Tcl, Perl, C/C++, shell, SQL, or…