CPU Physical Design Engineer

Staff Physical Design Engineer – CPU PPA Optimization

Location:

Portland, OR or Austin, TX

We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient processors.

Own and drive physical implementation from RTL-to-GDSII, focusing on PPA trade-offs.

Develop and optimize tool flows and methodologies for synthesis, place-and-route (PnR), clock tree synthesis (CTS), and timing closure.

Work closely with RTL designers to improve timing, area and power efficiency, and evaluate design changes and their impact on PPA.

Perform static timing analysis (STA), power analysis, signal integrity checks, and DFT implementation.

Optimize floor planning, clock distribution, power delivery networks, and congestion reduction strategies.

Automate design flows and methodologies to improve efficiency and scalability.

Minimum Qualifications:

Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field.

8+ years of experience in physical design with high frequency.

Strong expertise in Physical Design methodologies, tool flows, and PPA trade-offs.

Proficiency with EDA tools such as Synopsys (ICC2, Design Compiler, Prime Time), or Cadence (Innovus, Genus, Tempus).

Solid knowledge of place-and-route, clock tree synthesis, timing closure, and physical verification.

Hands‑on experience with power analysis, leakage optimization, and multi‑corner multi‑mode (MCMM) constraints.

Knowledge of DFT, ECO implementation, and signoff flows.

Understanding of low‑power design techniques such as clock gating, power gating, multi‑Vt optimization and multi‑power domain.

Proficiency in reading RTL (Verilog/VHDL) and understanding logic design.

Strong scripting skills in Python, Tcl, or Perl for tool automation and data analysis.

Excellent problem‑solving skills and ability to work in a cross‑functional team environment.

Preferred Qualifications:

Experience in advanced process nodes (5nm, 3nm, or below).

Competitive salary and benefits package.

Opportunities for professional growth in an innovative startup environment.

Collaboration with talented engineers passionate about cutting‑edge CPU technologies.

A flexible and inclusive work culture based in Portland, OR or Austin, TX.