Hardware Design Engineer - Sr

Hardware Design Engineer - Sr Staff

Join to apply for the Hardware Design Engineer - Sr Staff role at Qualcomm.

• Engineering Group, Engineering Group >
  Hardware Engineering

• Qualcomm Technologies, Inc.

Qualcomm Cloud System Hardware and Validation Engineering develops cutting‑edge rack‑level AI inference solutions for next‑generation liquid‑cooled data centers. As part of its rapid expansion, the team seeks experienced engineers to contribute to the next round of innovative AI products that Qualcomm intends to bring to market.

Design and develop motherboards, add‑in cards, and modules for Qualcomm’s new AI System On Chip (SoC)/System In Package (SIP). Primary responsibilities include working with cross‑functional teams (mechanical, thermal, SI, PTE, regulatory, validation, manufacturing, etc.) to execute projects from concept to production. Support rack‑level design and integration of cards, servers, and networking switches.

• Lead schematics design, PCB layouts, design reviews, component selections, mechanical and thermal designs, and develop test plans.
• Co‑develop functional specifications for systems, cards, sub‑systems, and rack‑level architectures.
• Collaborate with internal teams and ODMs to develop and support customer‑specific hardware and system requirements.
• Facilitate consensus on technical trade‑offs at hardware, software, and chip design levels.
• Support architecture and card designs including accelerator SoCs, memory, I/O, power delivery, electrical/mechanical integration, and PCB definition/design.
• Participate in the design and development of rack‑level inference solutions, ensuring alignment with customer requirements and system‑level performance goals.
• Resolve architecture and design issues across system, card, and rack levels.
• Assist in the bring‑up and debugging of hardware systems, cards, and rack‑level configurations.
• Provide technical oversight of factory and manufacturing processes, ensuring quality and consistency across rack‑level deployments.
• Contribute to writing Statements of Work (SOWs) and ODM product requirements; drive technical milestones and deliverables.
• Coordinate across multiple development sites, including Qualcomm locations and ODM/JDM partners in Taiwan and internationally.
• Travel to development and customer sites as needed to support rack‑level solution deployment and validation.
• Influence and communicate technical recommendations across disciplines and geographic locations.
• Coordinate and deliver technical training for ODMs, focusing on rack‑level system integration and deployment.

• System/card/rack‑level development, including architecture, design, validation, and deployment of enterprise‑class hardware platforms.

• Proven experience in rack‑level system integration, including chassis, backplane, cabling, airflow, and thermal management across multiple cards/modules.
• Familiarity with rack‑scale power delivery, including PDUs, VRMs, PMICs, and power budgeting across multiple boards.
• Experience with rack‑level diagnostics and bring‑up, including debug of interconnects, signal integrity across long traces/cables, and system‑level validation.
• Understanding of rack‑level mechanical constraints, EMI shielding, and compliance with data center deployment standards.
• Collaboration with ODMs/OEMs on rack‑level design and manufacturing, including review of mechanical drawings, thermal simulations, and compliance testing.

• Deep knowledge of PCIe cards, motherboards, daughter cards, and backplane signal and power delivery.
• Expertise in chassis design, airflow optimization, and thermal management.
• Solid understanding of system software operation from boot loader to OS and application layers.

• Experience qualifying PMICs, voltage regulators (VRs), clock buffers, flash memory, and connectors for use in complex card and rack‑level designs.

• Hands‑on experience in dense, high‑layer count PCB designs (8–20+ layers).
• Skilled in PCIe add‑in card/module design, debugging in high‑performance systems (x86 and ARM).
• Familiarity with JTAG tools for bring‑up and…