Silicon Physical Design Engineer V - ASIC Power Engineer

• ASIC Power Engineer to perform power analysis and optimizations in ASIC for Client's AR/VR products.
• Areas of interests includes Machine Learning. Primary languages are Python, TCL and System Verilog.

10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer

• BS in Electrical Engineering/Computer Science or equivalent experience

• Set up and maintain PPRTL and PTPX power analysis flows (average and time-based/peak power).
• Generate and manage activity inputs (FSDB/VCD/SAIF) from RTL and gate-level simulations; handle long-waveform and windowed analysis.
• Correlate RTL-level power estimates against gate-level signoff power and explain deltas.
• Produce per-block, per-hierarchy, and per-workload power breakdowns; identify top power contributors and clock/datapath waste.
• Recommend and evaluate power reduction opportunities (clock gating efficiency, datapath gating, memory power, idle leakage).
• Automate flows and reporting with TCL, Python, and Make-based build systems; integrate into regression/CI.
• Document methodology and support design teams in interpreting results.
• Perform PPA optimization with Fusion compiler.
• Perform RTL and netlist level Power analysis
• Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction
• Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing).
• Implement some blocks at RTL and UPF
• Ability to document and communicate clearly

• 10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer
• Experience with power estimation tools and synthesis, some physical design
• Knowledge of power trade-offs in design and back end implementation
• Hands-on experience in scripting, data analysis
• BS in Electrical Engineering/Computer Science or equivalent experience

• Hands-on production experience with Synopsys (PPRTL, PTPX/Prime Power, VCS, Verdi, DC, ICC, FC) and/or Cadence (Joules), Powr Artist
• Ability to debug simulation-to-power flow issues end to end.
• Strong scripting: TCL, Python and Excel based scripting and data-post-processing tools, model fitting, data visualization and analysis; comfortable with Linux and large compute/job-scheduling environments.
• Experience in low power design, tools and methodologies including power intent UPF specifications Silicon Power Characterization
• Some power modeling/profiling experience at IP/SoC level

How many rounds of interviews? 1-2 zoom interviews

45 mins