ASIC​/FPGA Design Engineer; Compute Test Division; North Reading, MA

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Date: Aug 26, 2025

Location: North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together,Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose
TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

Our Hardware Engineering team is seeking an FPGA/ASIC Design Engineer to work with a multi-disciplined team to design, code, and verify FPGAs in our cutting-edge products in a fast-paced, process-oriented environment.

• Deriving requirements from higher level specifications
• Designing and implementing register-transfer-level (RTL) code using Verilog
• Designing with Vendor IPs and various industry standard interface protocols
• Use of digital simulation tools to verify designs.
• Creation of physical design constraints for placement, timing closure and CDC
• Implementation of designs into target technologies using synthesis and place and route tools
• Perform timing analysis using static timing analysis tools.
• Perform lab debug of designs with laboratory equipment such as Logic Analyzers and oscilloscopes.
• Collaboration with other logic designers, board designers, software designers and ASIC designers
• Communicating status to project leadership

All About You
We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

• BS/MS in Electrical Engineering
• Minimum of 2+ years of industry experience
• Experience in logic design writing RTL in Verilog HDL
• Familiarity with a scripting language such as Python, TCL and Perl
• Experience with physical design tools from FPGA vendors (Vivado or Quartus) or ASIC vendors.
• Ability to debug difficult problems using a variety of software and hardware tools (debugger, JTAG emulator, logic analyzer, and oscilloscope)
• Highly motivated, team player, willing to pick up any piece of code, with a can-do attitude, and attracted to challenging opportunities
• Excellent written and oral communication skills
• Familiarity with high-speed serial protocols including PCIe and Ethernet.
• Familiarity with a digital simulation tool such as Synopsys, Cadence, or Mentor
• Familiarity with C/C++
• Familiarity in the use of a source control tools
• Familiarity working in a Linux based development environment

This position is not eligible for visa sponsorship

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please  to see details.

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