FPGA​/ASIC Design Engineer — RTL, Timing & Debug

A global test and automation company in Reading, MA is looking for an FPGA/ASIC Design Engineer. In this role, you will design, code, and verify FPGAs for cutting-edge products. The ideal candidate will have a BS/MS in Electrical Engineering, at least 2 years of experience in RTL coding with Verilog, and familiarity with design tools. Teradyne offers robust benefits, including medical, dental, and retirement plans.
#J-18808-Ljbffr