Junior FPGA Engineer: Build -Speed Test Platforms

Teradyne in North Reading, MA seeks a junior FPGA engineer to design and deliver high-performance FPGA-based solutions for test platforms. You will work with senior engineers on high-speed interfaces and system constraints.

You will apply Verilog/System Verilog, develop TCL/Python scripts, and collaborate across hardware, software, and verification teams. On-site three days a week, visa sponsorship not provided.

This is a strong opportunity to take on the Junior FPGA Engineer:
Build High-Speed Test Platforms role at Teradyne.

Are you ready to take on the Junior FPGA Engineer:
Build High-Speed Test Platforms role at Teradyne?

We would love to welcome a new Junior FPGA Engineer:
Build High-Speed Test Platforms to our group in Reading, MA, United States.

For the Junior FPGA Engineer:
Build High-Speed Test Platforms position at Teradyne, we are reviewing applications now.