Senior ASIC Verification Lead - SystemVerilog/UVM
Listed on 2026-10-07
-
Engineering
Test Engineer, Hardware Engineer
Teradyne is seeking a Sr. ASIC Verification Engineer in North Reading, MA to lead verification planning and develop advanced verification environments for complex ASIC/SoC designs.
You will collaborate with design, firmware, software, and validation teams to ensure comprehensive coverage and high-quality outcomes. The role requires 8+ years in ASIC/SoC verification, strong SystemC, C++, System Verilog/UVM experience, and knowledge of functional verification methodologies.
The Senior ASIC Verification Lead
- System Verilog/UVM role at Teradyne is now open for applications in Reading, MA, United States.
We are seeking a motivated Senior ASIC Verification Lead
- System Verilog/UVM to join Teradyne in Reading, MA, United States.
Consider building your career as a Senior ASIC Verification Lead
- System Verilog/UVM at Teradyne.
The Senior ASIC Verification Lead
- System Verilog/UVM position in the Engineering field is open for applications.
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