Senior ASIC Verification Engineer – SoC & UVM Expert
Listed on 2026-10-16
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Engineering
Test Engineer
Teradyne in North Reading, MA, seeks an experienced ASIC Verification Engineer to join the Reference Model team. You will design verification strategies, develop SystemC and System Verilog/UVM environments, and collaborate with design, firmware, software, and validation teams to ensure quality and timely delivery.
Ideal candidates hold a BS in a technical field, 4+ years of ASIC/SoC verification, and strong skills in SystemC, C++, Python, and UVM.
This posting is for the Senior ASIC Verification Engineer – SoC & UVM Expert role at Teradyne, based in Reading, MA, United States.
Our group is growing, and we are hiring a Senior ASIC Verification Engineer – SoC & UVM Expert in Reading, MA, United States.
This role is for the Senior ASIC Verification Engineer – SoC & UVM Expert role at Teradyne.
We are seeking a motivated Senior ASIC Verification Engineer – SoC & UVM Expert to join Teradyne in Reading, MA, United States.
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