Lead Analog Layout Engineer -Speed AI Interconnects
Kandou is seeking an Analog Layout Engineer (Lead) to drive custom analog layout and verification for high-speed Ser Des and memory interfaces across 28nm to 7nm nodes. You will collaborate with design teams to implement robust layouts, ensure IP and chip integration, and engage with customers on requirements and IP delivery.
The role demands hands-on experience in analog layout and strong communication skills in a fast-paced semiconductor environment. EU/CH/UK location flexibility is offered.
For the Lead Analog Layout Engineer for High-Speed AI Interconnects position at Kandou AI, we are reviewing applications now.
This is a great role to take on the Lead Analog Layout Engineer for High-Speed AI Interconnects role at Kandou AI.
As a Lead Analog Layout Engineer for High-Speed AI Interconnects, you will play an important part at Kandou AI in Reading, England, United Kingdom.
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