Senior Design Verification Engineer

Design Verification Engineer

Location:

Redmond, Seattle, Washington

• Design Verification expertise in System Verilog/UVM for unit/module level verification
• Lead Design Verification team (minimum 5 members)
• Develop UVM test benches from scratch
• Integrate VIPs and bring up test environments
• Port existing Verilog/VHDL environment to UVM-based environment
• Plan tests, code coverage, and debug verification issues
• Deep knowledge of AMBA protocol is required

• 8‑15 years of experience in design verification
• Hands‑on experience with System Verilog/UVM
• Leadership experience in a verification team
• Experience with VIP integration and bring up
• Proficiency in test planning, coverage coding, and debugging
• Strong understanding of AMBA protocols

Mid‑Senior level

Contract

Information Technology