Design Verification Engineer
Listed on 2026-01-03
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Engineering
Systems Engineer, Software Engineer
Summary: Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta’s Wearable devices that blend our real and virtual worlds throughout the day.
We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.
Define and implement verification plans, and build test benches for block, IP, sub-system, and SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
2+ years of hands-on experience in System Verilog/UVM methodology or C/C++ based verification
2+ years experience in block/IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Experience with revision control systems like Mercurial(Hg), Git or SVN
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch
Experience verifying ARM/RISC-V based sub-systems and So Cs
Experience verifying CPU/GPU designs
Experience in one or more of the following areas:
System Verilog Assertions (SVA), Formal, and Emulation
Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycle
$114,000/year to $166,000/year + bonus + equity + benefits
Equal OpportunityMeta is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics.
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