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Job Description & How to Apply Below
Ciena seeks a motivated engineer to join its verification team. In this full-time position, you will collaborate with digital design engineers and architects to validate architectural functional blocks through simulations. The ideal candidate will possess strong problem-solving skills and familiarity with formal verification methods, ensuring Ciena's high-speed connectivity advancements.
Key Responsibilities:
• Propose innovative verification strategies for Wavelogic products
• Create effective testbench environments using System Verilog UVM
• Validate architectural blocks through simulations and formal methods
• Collaborate with systems engineers to meet functionality requirements
• Monitor regressions, debug failures, and report status updates
Requirements:
• BEng/BSc or MEng/MSc in Electrical/Computer Engineering
• Experience with programming languages: C, C++, Python
• Familiar with standards like OTN and Ethernet
• Strong organizational and interpersonal skills
• Self-starter with a teamwork mentality
Join Ciena and contribute to shaping the networking future in telecommunications.
Position Requirements
10+ Years
work experience
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