Design Architect

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The High-Performance Integrated Group (HIG) within the Technology and Products Group (TPG) develops and optimizes High Bandwidth Memory (HBM) solutions for AI and ML applications. Our mission is to deliver the lowest power per bit solutions in the industry.

We are looking for an HBM IO Architecture Design engineer to own the development of the PHY IO on the interface die in HBM products. In this position, you will be responsible for defining design target, developing specifications, architecting IO/clocking/data path, and overseeing design, optimization, and verification. Use of both analog and digital CMOS design skills will be needed to work on the various circuits you would be responsible for.

You will be part of a highly multi‑functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to implement a common goal of ensuring our future HBM roadmap is successful.

• Define design targets and develop specifications for IO architecture
• Architect IO, clocking, and datapath for HBM products
• Plan IO development for next‑generation products
• Collaborate with Product Engineering to correlate silicon measurements and simulations
• Ensure design quality through engagement with Standards, CAD, modeling, and verification teams
• Drive innovation for future memory generations
• Contribute to cross‑group communication for standardization and success
• Perform optimization and verification of IO circuits

• MS or PhD in Electrical Engineering
• Minimum 10+ years of relevant engineering or design experience
• Expertise in high‑speed clocking design at 16
  
  Gbps+
• Strong knowledge of IO design principles and trade‑offs (speed, area, power, complexity)
• Familiarity with off‑chip protocols (UCIe, HBM, DDR, PCIe, MIPI, etc.)

• Hands‑on experience with FinFET device characteristics
• Prior circuit debug experience through Product Engineering or equivalent
• Deep understanding of signal integrity, channel characteristics, and ESD design techniques

• Seniority level:
  Mid‑Senior level
• Employment type:
  
  Full‑time
• Industry: Semiconductor Manufacturing
• Location:
  
  Richardson, TX

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