MTS IO Design Architect, HBM

Overview

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The High-Performance Integrated Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications. Our ultimate goal is to deliver the lowest power per bit solutions in the industry!

We are looking for an HBM IO Architecture Design engineer to own the development of the PHY IO on the interface die in HBM products. In this position, you will be responsible for the development including defining design targets, developing specs, architecting IO/clocking/datapath, and being responsible for design, optimization, and verification. Use of both analog and digital CMOS design skills will be needed to work on the various circuits you would be responsible for.

You will be part of a highly multi-functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to implement a common goal of ensuring our future HBM roadmap is successful.

• High-speed IO design architecture for HBM products
• Planning IO development on next generation products, set design target of each IO and IO related block
• Work with Product Engineering to correlate silicon measurements and simulation performance for circuit level design analysis
• Contribute to cross group communication to work towards standardization and group success
• Proactively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality
• Drive innovation into the future Memory generation with dynamic work environment

• Prior industrial experience in high-speed clocking design at 16
  
  Gbps+ speed
• Prior experience in system level IO timing budgeting
• Proven knowledge of IO design principles for practical design tradeoffs on speed/area/power/complexity
• Familiar with one or more off-chip protocols such as UCIe, HBM, DDR, PCIe, MIPI, etc
• Strong communication skills with the ability to clearly convey sophisticated technical concepts to other design peers both verbally and written
• Good understanding on FinFET device characteristics and hands-on design experience
• Deep understanding of signal integrity, channel characteristics, and ESD design techniques and topologies
• Excellent problem-solving and analytical skills
• Prior circuit debug experience through Product Engineering or equivalent preferred
• D2D design experience is a plus

• MS or PhD in EE
• Minimum 10+ years of proven experience in relevant Engineering or Design Engineering experience

Job title and level can scale depending on experience and qualifications.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.

Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on the Micron careers site.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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