Principal Digital IC Design Engineer

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Experience Level: Professional

Job Type: Regular

Location:

Richardson, TX, US, 75081

Requisition

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit  to learn how our innovative team is helping connect, protect and power our planet.

We are seeking a experienced and visionary Principal ASIC Engineer to lead our next-generation silicon development. In this high-impact technical leadership role, you will own the full-flow ASIC development lifecycle, driving projects from initial architectural concepts and RTL design down to physical sign-off and silicon bring-up.

The ideal candidate possesses deep expertise across both front-end design and back-end implementation, serving as a strategic authority who bridges the gap between hardware architecture, microarchitecture, and complex physical layout constraints.

Technical Leadership & Strategy

• Define, establish, and optimize cutting-edge ASIC design methodologies and full-flow architectures across the organization.
• Act as the chief technical authority to align cross-functional domains including Architecture, RTL Design, Verification, and Physical Design.
• Provide expert guidance on complex engineering trade-offs evaluating Power, Performance, and Area (PPA).

• Translate complex system-level product requirements into functional SoC/ASIC microarchitectures.
• Write high-quality, scalable, and synthesizable hardware description code using System Verilog/Verilog.
• Collaborate closely with Design Verification (DV) teams to review test plans and implement advanced Design for Testability (DFT) structures

• Drive full chip-level and block-level execution through synthesis, floor planning, and automated Place & Route (P&R) flows.
• Formulate and sign off on rigorous Timing Constraints and execute deep Static Timing Analysis (STA) to resolve setup/hold violations.
• Oversee structural physical verification including DRC, LVS, and ERC checks to guarantee tape-out readiness.

Education & Experience

• Bachelor’s degree in Electrical Engineering
• 12+ years of expereince or equivalent amount of advanced education and experience in direct, practical industry experience in digital ASIC design and implementation with a proven history of multiple successful commercial tape-outs.
• Hardware
  
  Languages:
  
  Mastery of System Verilog and Verilog.
• Full-Flow Implementation:
  Comprehensive hands-on command of the RTL-to-GDSII flow (Logic Synthesis, Floor planning, CTS, P&R, STA, and Physical Verification).
• EDA Tool Ecosystems:
  Deep proficiency with flagship EDA toolsuites from Synopsys (Design Compiler, IC Compiler II, Prime Time) or Cadence (Genus, Innovus, Tempus).
• Scripting & Automation:
  Strong programming proficiency in Python, TCL, and Bash/Perl for methodology customization and CAD data manipulation.
• Post-Silicon Execution:
  Direct experience with actual silicon bring-up, hardware debugging, and lab evaluation.

• Strong mentorship capabilities with a track record of leveling up senior and mid-level engineering talent.
• Excellent written and verbal communication skills, with the ability to articulate highly abstract hardware complexities to non-technical stakeholders