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Sr Principal Mixed Signal Verification Engineer
Job in
Richardson, Dallas County, Texas, 75080, USA
Listed on 2026-10-16
Listing for:
Peyton Resource Group
Full Time
position Listed on 2026-10-16
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer, Systems Engineer
Job Description & How to Apply Below
Senior Principal Mixed-Signal Verification Engineer
Experience: Senior-level, 15+ years
Position SummaryLead top-level design verification for mixed-signal and power-management ICs, ensuring functional accuracy, performance, and manufacturability across diverse applications.
Key Responsibilities- Develop and execute metric-driven verification plans based on functional, performance, and test specifications.
- Create constrained-random tests, automated checkers, and coverage models within UVM environments.
- Develop accurate RNM and Verilog-AMS models for top-level simulations.
- Verify power-management ICs, including motor drivers, battery management, DC-DC regulators, and power-loss protection.
- Collaborate with design and test teams to debug issues and improve first-pass silicon success.
- Automate verification processes and continuously improve methodologies.
- Support customer-facing technical discussions and use-case-driven verification.
- Bachelor’s degree in Electrical Engineering or a related field.
- 15+ years of experience in analog/mixed-signal design verification or power-management IC development, or equivalent education and experience.
- Strong expertise in UVM, test development, functional coverage, and global checkers.
- In-depth knowledge of analog and power-management circuits, including LDOs, amplifiers, bandgaps, DC-DC regulators, oscillators, and asynchronous state machines.
- Experience with SPICE/Spectre, event-based simulators, mixed-signal co-simulation, and simulation and silicon debugging.
- Excellent analytical, problem-solving, communication, and collaboration skills.
- Master’s degree in Electrical Engineering or a related field.
- Experience with top-down design and verification methodologies.
- Proficiency in Python or shell scripting.
- Familiarity with SV-UDN/EENET modeling, System Verilog assertions, and functional coverage.
- Experience with GUI-based and command-line simulation workflows.
- Understanding of AI integration into verification workflows.
Travel: Up to 10% domestic or international travel.
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