Interface Design Architect,HBM - DMTS Job Richardson area,Texas USA,Engineering

Responsibilities Will Include, But Are Not Limited To

Own and deliver critical HBM IO blocks and subsystems from architectural definition through circuit and RTL implementation, verification, tape-out, silicon bring-up, and post-silicon debug, including interfaces supporting future CPO systems.
Define HBM PHY, controller-to-PHY, die-to-die, clocking, training, calibration, power-management, error-handling, and test requirements for advanced heterogeneous systems.
Drive robust, high-performance builds by balancing bandwidth, latency, power, area, reliability, electrical signal quality, power stability, yield, and manufacturability trade-offs.
Lead architecture and design of analog, mixed-signal, and digital interface functions used in high-speed memory subsystems.
Partner with package, interposer, physical design, signal integrity, power integrity, and thermal teams to optimize interface implementation across 2.5D and 3D systems.
Lead root-cause analysis and resolution of complex pre-silicon and post-silicon issues across circuit design, RTL, architecture, process, package, interposer, and system interactions.
Serve as technical project lead for one or more advanced interface programs, coordinating execution across architecture, design, layout, verification, validation, packaging, test, and product engineering teams.
Define and communicate technical priorities, interface specifications, execution plans, risks, dependencies, and schedule impacts.
Work with internal teams, customers, IP providers, foundries, and ecosystem partners to define and integrate high-speed memory and die-to-die interface solutions.
Research, develop, and influence next-generation HBM, CPO, chiplet, and heterogeneous-integration architectures aligned with artificial intelligence, machine learning, and high-performance computing workloads.
Apply deep knowledge of DRAM operation, HBM and DDR interfaces, JEDEC specifications, mixed-signal design, memory subsystems, and high-speed interfaces to architect scalable solutions.
Mentor engineers through architecture reviews, build reviews, and hands‑on problem‑solving while improving build methods, guidelines, IP reuse, and execution rigor.

Minimum Qualifications

18+ years of experience in HBM, DDR, LPDDR, advanced memory, high-speed PHY, mixed‑signal design, system-on-chip, or application‑specific integrated circuit design roles.
Proven experience delivering complex interface IP or subsystems from architecture through silicon bring‑up and post‑silicon debug.
Strong expertise in high‑speed memory‑interface architecture and design, preferably including HBM product families.
Extensive experience with analog and mixed‑signal circuit design, digital microarchitecture, RTL design, clocking, training, calibration, power management, and error handling.
Experience with front‑end implementation and verification, including synthesis, static timing analysis, logic equivalence, and RTL debug.
Demonstrated technical project leadership across multidisciplinary and multi‑site engineering teams.
Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications

Direct experience architecting or developing HBM PHYs, DDR or LPDDR PHYs, or complete PHY and controller subsystems.
Experience with CPO system architecture, optical‑engine electrical interfaces, silicon‑photonics integration, or high‑speed Ser Des.
Experience with UCIe or other die‑to‑die interfaces and chiplet‑based architectures.
Experience with transistor‑level design and analog simulation tools such as FastSPICE, HSPICE, or similar.
Experience with digital design using Verilog, System Verilog, or similar RTL methodologies.
Exposure to 2.5D or 3D packaging technologies, including…

Interface Design Architect, HBM - DMTS