Senior Design Verification Engineer​/Architect, HBM

• Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs
• Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions
• Build and improve verification methodology components and GenAI applications aligned to HBM design cycles, broadening cross-disciplinary knowledge across custom digital and RTL2
  
  GDS flows
• Evaluate and debug pre-silicon and post-silicon issues in current HBM products, and contribute to exploration of new HBM verification architectures

• Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field
• 4+ years of relevant verification engineering experience, including 2 years in digital (Verilog), analog (Fast Spice), or mixed-signal verification (co-sims or real number modeling)
• Over 2 years working in custom design verification (schematic-based) or RTL design verification flows
• Ability to independently evaluate technical issues and define solutions, with good verbal and written communication skills

• Master's in Electrical Engineering, Computer Engineering, or related field, or equivalent experience, accompanied by more than 2 years in verification engineering roles
• One or more patents, trade secrets, or publications showcasing innovation and problem-solving in verification solutions
• Over 2 years in memory products using JEDEC specifications (preferably HBM), with experience building or improving verification flows
• Experience using AI-enabled or Generative AI solutions to accelerate verification planning, test development, coverage analysis, and root-cause debugging.

Systems Design Engineer 3 - Systems Design Engineer 4

Relocation Level: TBD

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