Electrical Schematic​/PCB Design Engineer; Semiconductor Test Hardware

Job Description

About the role:

We’re looking for an engineer who can translate customer inputs—Word specs, Excel netlists/BOMs, interface requirements, and legacy drawings—into robust electrical schematics that drive high‐quality PCB designs for semiconductor test hardware (probe, final test load boards, interface/fixture boards, handler interface, and related assemblies). You’ll own schematic capture and collaborate closely with PCB layout, mechanical, test, and manufacturing partners to deliver first‐pass success on fast‐moving customer programs.

What you’ll do:

• Own schematic capture from ambiguous or mixed customer inputs; clarify requirements, define architecture, and drive parts selection and library needs.

• Create well‐constrained designs that account for ATE realities (signal integrity, crosstalk, leakage, guarding/guard rings, Kelvin connections, relay/mux topologies, pogo/contactor constraints, ESD, thermal).

• Partner with PCB layout to enforce design rules for high‐density, high‐pin‐count boards (fan‐out, length/phase matching, differential pairs, controlled impedance, reference plane strategy, return current).

• Generate and maintain deliverables: schematics, netlists, constraints, design notes, BOMs, test points, release packages, and ECOs.

• Interface with customers (design reviews, DFM/DFT tradeoffs, risk/mitigation plans) and internal cross‐functional teams (ME, Test, Supply Chain, CM).

• Shepherd designs through build: fab/assembly bring‐up support, issue triage, corrective actions, and documentation updates.

• Continuously improve our libraries, checklists, and design standards for ATE hardware.

Required qualifications:

• 3–8+ years in electrical design for PCB‐based products; at least 2+ years specifically in semiconductor test hardware or high‐density mixed‐signal boards (probe/final test, load boards, DUT/contactor boards, or similar).

• Schematic capture proficiency in multiple CAD environments, including Cadence Allegro/Concept HDLOr Cad and Altium Designer (you can interpret and adapt across tools).

• Strong grasp of signal integrity and power integrity fundamentals: termination, return paths, reference plane stitching, decoupling strategy, controlled impedance, crosstalk mitigation.

• Experience with mixed‐signal and low‐leakage/low‐noise design (sensor or precision analog helpful), switch/mux/relay trees, level shifting, protection, and EMC/ESD practices.

• Comfortable reading/creating BOMs, netlists, constraints, and coordinating part selections with the library/CM team (second sources, life cycles, lead times).

• Ability to convert informal customer artifacts (spreadsheets, drawings, legacy PDFs) into a clean, reviewable schematic with clear notes/assumptions.

• Excellent documentation, version control, and ECO discipline; clear, concise communication with customers and vendors.

Nice to have:

• Background in ATE platforms (e.g., Advantest, Teradyne) and DUT/socket/contactor constraints.

• Experience with high‐current power distribution, RF/coax routing basics, or wide‐bandwidth measurement paths.

• Familiarity with DFM/DFT for probe and final test: stacking height, planarity, warpage, fiducials, test access, probe card specifics.

• Prior work with constraint‐driven flows (rules for length/phase, topology, via budgets) and SI/PI simulation tools (e.g., Sigrity, Hyper Lynx).

• Scripting/automation for CAD (Altium scripts, SKILL, Python) and PLM/ERP integration.

• Experience collaborating with overseas layout partners or CMs and doing supplier bring‐up.

What success looks like in 30 days:

• You’ve shipped at least one schematic package from customer inputs to layout handoff with zero critical ECOs.

• You’ve introduced at least one library or checklist improvement that reduces review time or rework.

• You’re the go‐to for translating messy specs into clear, test‐ready schematics.

Compensation & benefits:

• Competitive salary with performance bonus; 401(k) with match; paid time off and holidays.