HIG HBM Architecture

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Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Description:

As part of the High Bandwidth Memory (HBM) team, this role supports the development of sophisticated analog and mixed-signal circuitry used in next-generation memory PHYs and supporting infrastructure. The team collaborates across design, verification, packaging, and test to enable high-performance, scalable memory solutions and successful silicon bring-up.

In this role, the Analog Design Engineer contributes to the design, simulation, and validation of mixed-signal and PHY-adjacent circuit blocks. The position focuses on supporting modeling, simulation, integration, and debug efforts while building foundational expertise in analog, digital, and system-level design.

• Support design and integration of PHY-adjacent and base-die mixed-signal circuits, including schematic implementation and simulation
• Develop and maintain behavioral models using Verilog-A/AMS real-number modeling or System Verilog to support system-level verification
• Perform block-level SPICE and mixed-signal simulations, analyzing waveform behavior and corner-case scenarios
• Assist with validation activities including parasitic modeling, verification plan support, and calibration and adaptability checks
• Collaborate with multi-functional teams to support integration, simulation debug, and silicon bring-up readiness

• Bachelor’s or Master’s degree in Electrical Engineering or related field
• 5 years' experience in analog or mixed-signal design, verification, or PHY-adjacent development
• Strong understanding of device and circuit fundamentals including MOS behavior, biasing, gain, stability, and digital logic basics
• Familiarity with industry tools such as Cadence Virtuoso, Spectre, HSPICE, Xcelium/AMS, or VCS/Verdi
• Fundamental understanding of digital design concepts, including finite-state machines (FSMs), clock-domain crossing (CDC), reset synchronization, and pipelined architectures.
• Familiarity with RTL verification methodologies using System Verilog and exposure to UVM-based verification environments.
• Understanding of VLSI design flows, including simulation, synthesis, static timing analysis (STA), APR, and design verification.
• Experience using Linux-based development environments and version control systems.
• Strong analytical and debugging skills with the ability to identify and resolve design and verification issues.
• Experience using AI-Enabled or AI Assisted tools to support simulation, modeling, data analysis, or engineering productivity improvements

• Familiarity with Verilog-A/AMS, real-number modeling, or post-layout concepts such as parasitic extraction and analysis
• Exposure to statistical or Monte Carlo simulation techniques and mixed-signal verification workflows
  
  Experience with memory interfaces, HBM architectures, or mixed-signal IP integration through coursework or internships
• Exposure to high-speed interface concepts including clocking, jitter, termination, sensing, and calibration
• Background in lab bring-up, silicon debug, or simulation-to-silicon correlation
• Programming or scripting experience such as Python or MATLAB for automation and data analysis

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