Senior Lead, Hardware DFT & Testability Engineer; PCBA)

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Date: Oct 31, 2026

At Celestica, we don't just manufacture high-complexity technology, we design, engineer, and optimize the hardware powering the future. As a global leader in design, engineering, and manufacturing services, our teams partner with world-changing brands across cloud infrastructure, aerospace, defense, healthtech, and advanced electronics. Located in Richardson, TX, our site offers a collaborative, fast-paced environment where your technical voice directly impacts the physical products shaping tomorrow's technology landscape.

Celestica is seeking a Hardware DFT & Testability Engineer (PCBA) to ensure testability and maximum test coverage are embedded into printed circuit board (PCB) hardware designs long before layout freeze. In this role within our DFx Center of Excellence, you will serve as an upstream design gatekeeper. You will perform in-design testability reviews, audit physical test point access for In-Circuit Testing (ICT), configure board-level boundary scan chains, and model structural and functional test coverage against key manufacturing targets to drive high-yield, debug-ready releases.

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Note:

Candidates with strong hands-on backgrounds in structural In-Circuit Testing (ICT) fixture development—such as Teradyne, Keysight 3070, or flying probes—who wish to transition into upstream pre-layout design gatekeeping are highly encouraged to apply.)

Detailed Description

• Pre-Freeze Audits:
  Review electrical schematics and high-density PCB CAD layouts against the core DFT rule set prior to layout freeze. Enforce physical requirements such as test pad pitch, pogo-pin/probe-to-component clearances, and keep-out zones.
• Coverage Modeling:
  Model structural and functional coverage against the Manufacturing Test Requirements Specification (MTRS) and quantify coverage gaps before manufacturing begins.
• Finding Disposition:
  Partner directly with hardware design, PCB layout, and software teams to resolve testability issues through test point additions, boundary scan chain corrections, or agreed-upon design alternatives.
• Validation & Verification:
  Verify actual achieved coverage on the first physical test fixture (e.g., ICT, flying probe) and document discrepancies against pre-layout claims.
• Site Support:
  Assist with functional test definition and early build debug in collaboration with Technical Region Leads (TRLs) and local test SMEs on the manufacturing floor.
• Rule Evolution:
  Propose targeted DFT rule set updates derived from test escapes, physical fixture strain, and post-build rework.
• Formal testability reviews and fully dispositioned DFT findings prior to CAD freeze.
• Structural and functional coverage models mapped against the MTRS.
• Empirical evidence packages for achieved coverage on first fixtures.

Key Success Metrics

• Total designed-in coverage achieved on the first physical fixture.
• Complete resolution and closure of DFT findings prior to layout freeze.
• Minimization of test escapes and repeat testability issues across product lines.
• Must-Have:
  Strong background in board-level Design for Testability (DFT), electronic schematics, and high-density PCB layout checks.
• Highly Valued:
  Hands-on experience with In-Circuit Testing (ICT) platforms (e.g., Keysight 3070, Teradyne Test Station, Takaya flying probe), including an understanding of bed-of-nails fixture constraints.
• Core Technical
  
  Skills:
  
  Experience evaluating multi-device IEEE 1149.1 Boundary Scan / JTAG chains, debug/provisioning access, and test point physical accessibility.
• Coverage Expertise:
  Practical knowledge of MTRS coverage modeling, functional test strategy, and hardware bring-up.
• Out of Scope
  :
  Experienc…