Senior FPGA Engineer: RTL, Verification & Debug Lead
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Engineering
Job Description & How to Apply Below
Celestica Inc. in Richardson, TX is seeking a Senior Staff FPGA Engineer to drive RTL design, verification, and back‑end flow for advanced hardware platform solutions.
You will collaborate with platform architects, board designers, and software teams to ensure robust delivery and timely debugging on real hardware.
Required:
12+ years in FPGA design; strong Verilog/System Verilog; experience with Xilinx/Intel FPGAs, PCIe, DDR, LVDS; familiarity with UVM and Model Sim/Vivado/Quartus; excellent
We are seeking a motivated Senior FPGA Engineer: RTL, Verification & Debug Lead to join Celestica Inc. in Richardson, TX, United States.
The Senior FPGA Engineer: RTL, Verification & Debug Lead role at Celestica Inc. is now open for applications in Richardson, TX, United States.
Join us at Celestica Inc. as our next Senior FPGA Engineer: RTL, Verification & Debug Lead in Richardson, TX, United States.
Position Requirements
10+ Years work experience(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
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