SoC Physical Design Formal Verification Engineer, HBM

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Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities.

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As an SoC Physical Design Formal Verification Engineer in the Heterogeneous Integration Group (HIG), you will own the formal verification signoff of advanced HBM SoC logic/base die designs as they move from RTL through synthesis, DFT insertion, place-and-route, and ECOs to tapeout. You will work closely with RTL design, physical design, DFT, low-power, and STA teams to ensure every implementation step preserves functional intent and power intent.

This is a hands-on role with opportunities to own block and full-chip formal signoff and shape formal methodology across multiple product generations.

Key Responsibilities Own formal equivalence checking (LEC) for HBM SoC blocks and full-chip across the implementation flow, including RTL-to-netlist, netlist-to-netlist (post-synthesis, post-DFT insertion, post-CTS, post-route), and ECO netlists.

Develop and maintain robust equivalence setups, including handling of retiming, clock gating, multibit banking, constant/unreachable register optimization, scan and MBIST insertion, and black-boxed hard IP.Debug and resolve non-equivalence and abort points efficiently, partnering with RTL, synthesis, DFT, and physical design teams to root-cause issues and converge designs to clean signoff.

Perform static low-power verification (e.g., Conformal Low Power, VC LP) against UPF power intent, covering isolation, level shifting, retention, power switches, and always-on connectivity through implementation.

Drive functional ECO generation and implementation using formal ECO tools (e.g., Conformal ECO, Formality ECO), minimizing patch size and physical impact late in the design cycle.

Run and review netlist-level structural and formal checks such as CDC/RDC, X-propagation, and connectivity checks as required by signoff criteria.

Define formal verification signoff criteria, checklists, and QoR metrics, and represent formal verification status in tapeout readiness reviews.

Build and improve automated formal verification flows and regression infrastructure using Python, TCL, and shell to improve runtime, capacity, and debug productivity.

Collaborate with EDA vendors to resolve tool issues, evaluate new capabilities, and adopt best-in-class methodology across product generations.

Develop agentic AI flows based on latest LLM and Gen-AI capabilities.

Required Qualifications Strong hands-on experience with formal equivalence checking on complex SoC designs at advanced process nodes.

Proficiency with industry formal verification tools (e.g., Cadence Conformal LEC/LP/ECO, Synopsys Formality/VC LP, Siemens Questa or equivalent).Solid understanding of the RTL-to-GDSII implementation flow, including synthesis, DFT insertion, placement, CTS, routing, and ECO flows, and how each step impacts equivalence.

Experience debugging non-equivalence, aborts, and setup issues caused by synthesis optimizations such as retiming, register merging, clock gating, and multibit flops.

Working knowledge of power…